A composite video signal contains information which is used by a video system to generate a video picture on a display, monitor or television. Each period, within the horizontal portion of a composite video signal contains information representing one horizontal output line which is to be output on the video display, monitor or television. Each horizontal period includes a horizontal synchronization pulse, a burst signal and a video information signal. In many video transmission systems, color or chrominance information is represented by a particular phase of the chrominance subcarrier signal that is amplitude modulated with color information. The horizontal synchronization pulse is used by a phase locked loop to synchronize the system for displaying the next horizontal line of video information. The burst signal is used to synchronize the phase of the sampling pulses with the phase of the color subcarrier signal. The burst signal has a burst signal frequency equal to 3.58 MHz, which is the frequency of the chrominance subcarrier f.sub.sc. The video information signal then comprises the chrominance subcarrier having different phases amplitude-modulated with chrominance information. The composite color video signal includes both luminance and chrominance information.
A video encoder circuit receives RGB video signals from a video source and encodes a composite video signal representing the RGB signals for transmission to other systems. The RGB video signals are typically encoded first into separate luminance Y and chrominance C signals. The separate luminance Y and chrominance C signals are then combined into the composite video signal. Different types of televisions, monitors and displays will accept the separate chrominance C and luminance Y video signals or the composite video signal CV. Accordingly, most video encoders provide the separate chrominance C and luminance Y video signals and the composite video signal CV, allowing the system designer the flexibility to use either the separate chrominance C and luminance Y video signals or the composite video signal CV.
Within the video signals, the values of the components are determined by their relative amplitude with respect to the blank or pedestal level. It is therefore essential that the blank or pedestal level is maintained at a known level so that the value of the components can be readily determined by the system. The blank level of a video signal is typically clamped to a known DC level allowing the values of the components within the signal to be determined by determining their amplitude with respect to the known DC level. The blank level of the separate chrominance C and luminance Y video signals must also be clamped to a known blank or pedestal level in order to determine the true values of their components.
A video encoder circuit of the prior art with four clamping circuits is illustrated in FIG. 1. The video encoder circuit receives an RGB signal and generates a composite video signal CV, a separate luminance video signal Y and a separate chrominance video signal C from the RGB signal. The RGB signal includes separate Red, Green and Blue signals which are combined within the encoder 10, into the separate luminance signal Y, by a Y-matrix circuit 12, and into the separate chrominance signal C, by the chrominance generation circuit 26. The separate luminance signal Y and the separate chrominance signal C are then combined by the composite video generation circuit 28 into the composite video signal CV. The Y-matrix circuit 12 mathematically multiplies each of the Red, Green and Blue signals by an appropriate weighting factor to obtain weighted signals, which are combined together to form the separate luminance signal Y. The equation implemented by the Y-matrix circuit is: EQU Y =0.30*R +0.59*G +0.11 *B (1)
Accordingly, in order to derive the separate luminance signal Y, the Red, Green and Blue input signals are combined according to equation (1 ), with the Red, Green and Blue signals comprising unequal components of the separate luminance signal Y.
When bringing electrical signals into a system from an outside system, it is typically necessary to shift the signals into an appropriate voltage range to compensate for any difference in signal voltage resulting from a difference in absolute ground potential between the two systems. This operation is performed by a clamping circuit which shifts the range of the signals into the range expected by the receiving system. For a video signal, as described above, such a clamping circuit will clamp the blank level of the signal to a known level, in order that the components of the signal can be readily determined.
As illustrated in FIG. 1, the clamping circuits 14, 16 and 18 are used to adjust the Red, Green and Blue input signals received from an outside system, to an appropriate level expected by the Y-matrix circuit 12. The clamping circuits 14, 16 and 18 shift the blank levels of the Red, Green and Blue input signals, respectively, to a known DC level.
The Y-matrix circuit 12 combines the clamped Red, Green and Blue input signals, in a weighted fashion according to equation (1), to form the separate luminance signal Y which is provided from the output of the Y-matrix circuit 12. After a delay 22, a fourth clamping circuit 20 is then used to shift the DC voltage level of the separate luminance signal Y provided from the Y-matrix circuit 12, before it is output from the video encoder circuit 10. The delay 22 is built into the separate luminance video signal Y path in order to compensate for the chrominance generation circuit 26 which takes a longer period of time to generate the separate chrominance signal C. In order to provide the separate chrominance signal C and the separate luminance signal Y to the composite video signal generation circuit 28 simultaneously, the delay 22 is incorporated after the separate luminance signal Y is generated by the Y-matrix circuit 12. After the delay 22 and the clamping circuit 20, the separate luminance signal Y is provided to a horizontal synchronization pulse generation circuit 24 for adding a horizontal synchronization pulse to the separate luminance signal Y, during the horizontal synchronization period. From the horizontal synchronization pulse generation circuit 24, the separate luminance signal Y, with horizontal synchronization pulse, is then provided as an output of the video encoder circuit and to the composite video signal generation circuit 28.
The clamping circuits 14, 16, 18 and 20 each require extra circuitry to be added to the video encoder circuit 10. Each clamping circuit typically includes a large capacitor which is external to the video encoder circuit 10. Not only do these large capacitors take up valuable space within the system, but when the video encoder circuit 10 is implemented within an integrated circuit, a pin for each of these external capacitors is required, thus increasing the necessary size of the video encoder circuit 10.
In order to drive state-of-the-art high performance monitors the clamping circuits must also be capable of passing signals at speeds of at least 33 MHz. Conventional approaches utilize a differential amplifier with high speed npn and pnp transistors to replicate the video signal for driving such high performance monitors. As is well known among those skilled in the art, such high-speed pnp transistors are expensive to include within a system or integrated circuit. Accordingly, such a conventional approach requires a relatively expensive process to manufacture and is still unable to meet the speed requirements for driving high performance monitors. What is needed is a clamping circuit which requires less external components, takes up less space and provides higher performance characteristics than conventional designs without using high speed pnp transistors.
In order to comply with the National Television Standards Committee (NTSC) video specifications, horizontal synchronizing pulses must be embedded in the video stream in order for the receiving systems to operate properly. These horizontal synchronizing pulses must also be set to exact levels in order to meet the NTSC specifications. A horizontal synchronization pulse is included within each horizontal period of an encoded video signal in order to allow the receiving system to synchronize to each horizontal line of video information within the encoded video signal.
The horizontal synchronization pulse is generated by the horizontal synchronization pulse generation circuit 24 and added to the separate luminance signal Y before it is provided to the composite video generation circuit 28. Typical prior art video encoder circuits generate exact horizontal synchronization pulse levels by first clamping the encoded video signal to a precise reference voltage level. Accordingly, during the time period when the horizontal synchronization pulse is to be added, the voltage of the encoded separate luminance video signal Y is exactly known by the system. A switching circuit, within the horizontal synchronization pulse generation circuit 24, is then used to switch to a steady, precise horizontal synchronization voltage level, during the horizontal synchronization time period. At the end of the horizontal synchronization time period, the switching circuit switches away from the steady, precise horizontal synchronization voltage level and back to the video signal. Accordingly, the resulting encoded video signal includes a horizontal synchronization pulse during the horizontal synchronization time period and the video signal during all other periods.
When generating horizontal synchronization pulses, a video encoder circuit, as described above, requires the generation of two precise voltage reference levels for clamping the encoded video signal to the precise reference voltage level and for generating the horizontal synchronization pulse at the horizontal synchronization voltage level. Because of the difficulty associated with generating such precise voltage levels within an integrated circuit, external components are required to generate the necessary voltage levels. The clamping circuit 20 is required to clamp the encoded video signal to the precise reference voltage level. A switching mechanism is also required to switch between the encoded video signal and the horizontal synchronization voltage level at the beginning of the horizontal synchronization pulse and to then switch back from the horizontal synchronization voltage level to the encoded video signal at the completion of the horizontal synchronization pulse. What is needed is a horizontal synchronization pulse generating circuit within a video encoder which does not require the clamping and switching circuitry and the generation of the precision voltage levels required by the video encoder circuits of the prior art.